1
GATE EE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The current state $${Q_A}{Q_B}$$ of a two $$JK$$ flip-flop system is $$00.$$ Assume that the clock rise-time is much smaller than the delay of the $$JK$$ flip-flop. The next state of the system is GATE EE 2016 Set 1 Digital Electronics - Sequential Circuits Question 8 English
A
$$00$$
B
$$01$$
C
$$11$$
D
$$10$$
2
GATE EE 2015 Set 1
Numerical
+2
-0
The figure shows a digital circuit constructed using negative edge triggered $$J-K$$ flip flops. Assume a starting state of $${Q_2}\,{Q_1}\,{Q_0} = 000.$$ This state $${Q_2}\,{Q_1}\,{Q_0} = 000$$ will repeat after _____ number of cycles of the clock $$CLK.$$ GATE EE 2015 Set 1 Digital Electronics - Sequential Circuits Question 10 English
Your input ____
3
GATE EE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is $${Q_1}{Q_0}$$ $$=00.$$ The state $$\left( {{Q_1}{Q_0}} \right),$$ immediately after the $${333^{rd}}$$ clock pulse is GATE EE 2015 Set 2 Digital Electronics - Sequential Circuits Question 9 English
A
$$00$$
B
$$01$$
C
$$10$$
D
$$11$$
4
GATE EE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A $$JK$$ flip flop can be implemented by $$T$$ flip flops. Identify the correct implementation.
A
GATE EE 2014 Set 2 Digital Electronics - Sequential Circuits Question 11 English Option 1
B
GATE EE 2014 Set 2 Digital Electronics - Sequential Circuits Question 11 English Option 2
C
GATE EE 2014 Set 2 Digital Electronics - Sequential Circuits Question 11 English Option 3
D
GATE EE 2014 Set 2 Digital Electronics - Sequential Circuits Question 11 English Option 4
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