1
GATE EE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The current state $${Q_A}{Q_B}$$ of a two $$JK$$ flip-flop system is $$00.$$ Assume that the clock rise-time is much smaller than the delay of the $$JK$$ flip-flop. The next state of the system is
![GATE EE 2016 Set 1 Digital Electronics - Sequential Circuits Question 9 English](https://imagex.cdn.examgoal.net/RD8nNdEeJB2QlI8zE/W5EeB7q7NVMweQWjrRXqim5RHTzvC/zA4e5LeMNdKcOEkaJ2X8ap/uploadfile.jpg)
2
GATE EE 2015 Set 2
MCQ (Single Correct Answer)
+2
-0.6
In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is $${Q_1}{Q_0}$$ $$=00.$$ The state $$\left( {{Q_1}{Q_0}} \right),$$ immediately after the $${333^{rd}}$$ clock pulse is
![GATE EE 2015 Set 2 Digital Electronics - Sequential Circuits Question 10 English](https://imagex.cdn.examgoal.net/05kkIJUbT7TeEFUIe/mhXL0m1x3u0oN3IIgY5LGaYW8ZoHw/59m868gcxt6dtZ8Xc7ZBa1/uploadfile.jpg)
3
GATE EE 2015 Set 1
Numerical
+2
-0
The figure shows a digital circuit constructed using negative edge triggered $$J-K$$ flip flops. Assume a starting state of $${Q_2}\,{Q_1}\,{Q_0} = 000.$$ This state $${Q_2}\,{Q_1}\,{Q_0} = 000$$ will repeat after _____ number of cycles of the clock $$CLK.$$
![GATE EE 2015 Set 1 Digital Electronics - Sequential Circuits Question 11 English](https://gateclass.cdn.examgoal.net/zQ3laJDKnhAWqft8q/hzJqWaKtlAEXojAD3L4IPBLHnSaQJ/Go50tfYqQim1MIZ9XvwEt3/uploadfile.jpg)
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4
GATE EE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
A $$JK$$ flip flop can be implemented by $$T$$ flip flops. Identify the correct implementation.
Questions Asked from Sequential Circuits (Marks 2)
Number in Brackets after Paper Indicates No. of Questions
GATE EE Subjects
Electromagnetic Fields
Signals and Systems
Engineering Mathematics
General Aptitude
Power Electronics
Power System Analysis
Analog Electronics
Control Systems
Digital Electronics
Electrical Machines
Electric Circuits