In the circuit, the present value of $Z$ is $1$. Neglecting the delay in the combinatorial circuit, the values of $S$ and $Z$, respectively, after the application of the clock will be

A MOD-2 and a MOD-5 up-counter when cascaded together results in a MOD _________ counter. (in integer).

The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns, is ________. (round off to one decimal place).

A 16 -bit synchronous binary up-counter is clocked with a frequency $f_{c l k}$. The two most significant bits are ORed together to form an output $Y$. Measurements shows that $Y$ is periodic and the duration for which $Y$ the remains high in each period is 24 ms . The clock frequency $f_{\text {clk }}$ is $\_\_\_\_$ MHz. (Round off to 2 decimal places)