GATE EE
Digital Electronics
Sequential Circuits
Previous Years Questions

## Marks 1

A MOD-2 and a MOD-5 up-counter when cascaded together results in a MOD _________ counter. (in integer).
The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns, is ____...
A cascade of three identical modulo -$$5$$ counters has an over all modulus of
A state diagram of a logic gate which exhibits a delay in the output is shown in the figure, where $$X$$ is the don't care condition, and $$Q$$ is the...
Consider the given circuit. In this circuit, the race around ...
The frequency of the clock signal applied to the rising edge triggered $$D$$ flip-flop shown in Fig. is $$10$$ $$kHz.$$ The frequency of the signal av...
For a $$J$$-$$K$$ flip-flop its $$J$$ input is tied to its own $$Q$$ output and its $$K$$ input is connected to its own $$Q$$ output. If the flip-flop...

## Marks 2

For the synchronous sequential circuit shown below, the output $$Z$$ is zero for the initial conditions $${Q_A}{Q_B}{Q_C} = Q{'_A}Q{'_B}Q{'_C} = 100.... The current state$${Q_A}{Q_B}$$of a two$$JK$$flip-flop system is$$00.$$Assume that the clock rise-time is much smaller than the delay of the$$J...
The figure shows a digital circuit constructed using negative edge triggered $$J-K$$ flip flops. Assume a starting state of $${Q_2}\,{Q_1}\,{Q_0} = 00... In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is$${Q_1}{Q_0}=00.$$The state$$\left( {{Q...
A $$JK$$ flip flop can be implemented by $$T$$ flip flops. Identify the correct implementation.
The clock frequency applied to the digital circuit shown in the figure below is $$1$$ $$kHz.$$ If the initial state of the output $$Q$$ of the flip-fl...
The state transition diagram for the logic circuit shown is ...
A two-bit counter circuit is shown below It the state $${Q_A}{Q_B}$$ of the counter at the clock time $${t_n}$$ is $$'10'$$ then the state $${Q_A}{Q... The digital circuit shown in the figure works as a ... Select the circuit which will produce the given output$$Q$$for the input signals$${X_1}$$and$${X_2}$$given in the figure. ... The shift register shown in Fig. is initially loaded with the bit pattern$$1010.$$Subsequently the shift register is clocked, and with each clock pu... A dual-slope analog-to-digital converter uses an$$N$$-bit counter. When the input signal$${V_a}$$is being integrated, the counter is allowed to cou... The counter shown in Fig. is initially in state$${Q_2} = 0,\,{Q_1} = 1,\,{Q_0} = 0.$$With reference to the$$CLK$$input, draw waveforms for$${Q_2}...

## Marks 5

The digital circuit shown in figure generates a modified clock pulse at the output. Choose the correct output waveform form the options given below. ...
The ripple counter shown in Fig. is made up negative edge triggered $$J$$-$$E$$ flips flops. The signal levels at $$J$$ and $$K$$ inputs of all the fl...
For the ring counter shown in Fig. find the steady state sequence if the initial state of the counters is $$1110\,\,(i.e.,\,\,{Q_3},{Q_2},{Q_1},{Q_0} ...$$(a)$$Construct the truth table for the circuit given in Figure$${Q_1},{Q_2}$$and$${Q_3} are outputs and the clock pulses are the inputs. Unuse...
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