Microprocessor · Digital Electronics · GATE EE

In $$8085A$$ microprocessor, the operation performed by the instruction $$LHLD$$ $${2100_H}$$ is

An input device is interfaced with Intel $$8085$$ $$A$$ microprocessor as memory mapped $${\rm I}/O,$$ the address of the device is $$2500H.$$ In order to input data from the device to accumulator, the sequence of instructions will be

When a program is being executed in an $$8085$$ microprocessor, its Program Counter contains

The logic circuit used to generate the active low chip select $$(CS)$$ by an $$8085$$ microprocessor to address a peripheral is shown in Fig. The peripheral will respond to addresses in the range.

Which one of the following is not a vected interrupt?

In a microprocessor, the address of the next instruction to be executed, is stored in

The range of address for which the memory chip shown in Figure, will be selected is .... to .........

In an $$8085$$ microprocessor, after the execution of $$XRA$$ $$A$$ instruction

The contents of the accumulator in an $$8085$$ microprocessor is altered after the execution of the instruction.

Three devices $$A,$$ $$B$$ and $$C$$ have to be connected to a $$8085$$ microprocessor. Device $$A$$ has highest priority and device $$C$$ has the lowest priority. In this context which of the following is correct assignment of interrupt inputs?

If the $$HLT$$ instruction of a $$8085$$ microprocessor is executed,

In a given 8-bit general purpose micro-controller there are following flags.

C-Carry, A-Auxiliary Carry, O-Overflow flag, P-Parity (0 for even, 1 for odd)

R$$_0$$ and R$$_1$$ are the two general purpose registers of the micro-controller.

After execution of the following instructions, the decimal equivalent of the binary sequence of the flag pattern [CAOP] will be _________.

MOV R0, +0x60

MOV R1, +0x46

ADD R0, R1

In an $$8085$$ microprocessor, the following program is executed

At the end of program, register $$A$$ contains

An output device is interfaced with $$8$$ bit microprocessor $$8085$$$$A.$$ The interfacing circuit is shown in figure

The interfacing circuit makes use of $$3$$ line to $$8$$ line decoder having $$3$$ enable lines $${E_1}\,\,\overline E {}_2,$$ $$\,\overline E {}_3$$. The address of the device is

A portion of the main program to call a subroutine $$SUB$$ in an $$8085$$ environment is given below:
$$\eqalign{ & LXI\,\,\,\,\,\,\,\,\,\,\,\,\,D\,\,\,DISP \cr & LP\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,CALL\,\,\,SUB \cr} $$

It is desired that control be returned to $$LP+DISP+3$$ when the $$RET$$ instruction is executed in the subroutine. The set of instructions that precede the $$RET$$ instruction in the subroutine are

When a $$''CALL$$ $$addr'$$ instruction is executed, the $$CPU$$ carries out the following sequential operations internally.

Note:
$$(R)$$ means content of register $$R$$
$$\left( {\left( R \right)} \right)$$ means content of memory locating pointed by $$R$$
$$PC$$ means Program Counter
$$SP$$ means Stack Pointer

In $$8085$$ microprocessor, the contents of the Accumulator, after the following instructions are executed will become

$$\eqalign{ & XRA\,\,\,A \cr & MVI\,\,\,B\,\,\,F0\,\,\,H \cr & SUB\,\,\,B \cr} $$

The contents (in Hexadecimal) of some of the memory locations in an $$8085A$$ based system are given below

The contents of stack pointer $$(SP),$$ program counter $$(PC)$$ and $$(HL)$$ are $$270H,$$ $$2100H$$ and $$0000H$$ respectively. When the following sequence of instructions are executed,
$$2100H:$$ $$DAD$$ $$SP$$
$$2101H;$$ $$PCHL$$

The contents of $$(SP)$$ and $$(PC)$$ at the end of execution will be

In an $$8085$$ $$A$$ microprocessor based system, it is desired to increment the contents of memory location whose address is available in $$(D,E)$$ register pair and store the result in same location. The sequence of instructions is

Which one of the following statements regarding the $$INT$$ (interrupt) and the $$BRQ$$ (bus request) pins in a $$CPU$$ is true?

The associated figure shows the two types of rotate right instruction $${R_1},\,{R_2}$$ available in a microprocessor where Register is a $$8$$-bit register and $$C$$ is the carry bit. The rotate left instructions $$L1$$ and $$L2$$ are similar except that $$C$$ now links the most significant bit of Register instead of the least significant one.

Suppose Register contains the $$2's$$ complement number $$11010110.$$ If this number is delivered by $$2$$ the answer should be

The associated figure shows the two types of rotate right instruction $${R_1},\,{R_2}$$ available in a microprocessor where Register is a $$8$$-bit register and $$C$$ is the carry bit. The rotate left instructions $$L1$$ and $$L2$$ are similar except that $$C$$ now links the most significant bit of Register instead of the least significant one.

Such a division can be correctly performed by the following set of operations

A software delay subroutine is written as given below:

How many times $$DCR$$ $$L$$ instruction will be executed?

The $$8085$$ assembly language instruction that stores the content of $$H$$ and $$L$$ registers into the memory locations $$2050H$$ and $$2051H,$$ respectively, is

The following program is written for an $$8085$$ microprocessor to add two bytes located at memory addresses $$1FFE$$ and $$1FFF$$
$$\eqalign{ & LXI\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,H,\,\,\,1FFE \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,B,\,\,\,M \cr & INR\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,L \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,A,\,\,\,M \cr & ADD\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,B \cr & INR\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,L \cr & MOV\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,M,\,\,\,A \cr & XRA\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,A \cr} $$

On completion of the execution of the program, the result of additional is found.

An Intel $$8085$$ processor is executing the program given below.
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,MVIA,\,\,10H \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,MVIB,\,\,10H \cr & BACK:\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,NOP \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,ADD\,\,B \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,RLC \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,JNC\,\,BACK \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,HLT \cr} $$

The number of times that the operation $$NOP$$ will be executed is equal to

The stack pointer of a microprocessor is at $$A001H.$$ At the end of execution of following instructions, the value of stack pointer is _____________
$$\eqalign{ & PUSH\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,PSW \cr & XTHL \cr & PUSH\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,D \cr & JMP\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,\,FC70H \cr} $$

In a $$8085$$ microprocessor, the following instructions may result in change of accumulator contents and change in status flags. Choose the correct match for each instruction.