Logic Families and Memories · Digital Electronics · GATE EE

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Marks 1

GATE EE 2005
If $${X_1}$$ and $${X_2}$$ are the inputs to the circuit shown in the figure, the output $$Q$$ is ...
GATE EE 1998
In standard $$TTL$$ gates, the totem pole output stage is primarily used to
GATE EE 1998
The open collector outputs of two$$2$$-inputs $$NAND$$ gates are connected to a common pull up resistor. If the input to the gates are $$P,Q$$ and $$R...

Marks 2

GATE EE 2010
The $$TTL$$ circuit shown in the figure is fed with the waveform $$X$$ (also shown). All gates have equal propagation delay of $$10$$ $$ns.$$ The outp...
GATE EE 2006
A TTL NOT gate circuit is shown in figure. Assuming $${V_{BE}} = 0.7\,v$$ of both the transistors, if $${V_i} = 3.0\,V,$$ then the states of the two t...
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