1
GATE EE 2012
MCQ (Single Correct Answer)
+2
-0.6
The state transition diagram for the logic circuit shown is GATE EE 2012 Digital Electronics - Sequential Circuits Question 13 English
A
GATE EE 2012 Digital Electronics - Sequential Circuits Question 13 English Option 1
B
GATE EE 2012 Digital Electronics - Sequential Circuits Question 13 English Option 2
C
GATE EE 2012 Digital Electronics - Sequential Circuits Question 13 English Option 3
D
GATE EE 2012 Digital Electronics - Sequential Circuits Question 13 English Option 4
2
GATE EE 2011
MCQ (Single Correct Answer)
+2
-0.6
A two-bit counter circuit is shown below GATE EE 2011 Digital Electronics - Sequential Circuits Question 14 English

It the state $${Q_A}{Q_B}$$ of the counter at the clock time $${t_n}$$ is $$'10'$$ then the state $${Q_A}{Q_B}$$ of the counter at $${t_n} + 3$$ (after three clock cycles) will be

A
$$00$$
B
$$01$$
C
$$10$$
D
$$11$$
3
GATE EE 2005
MCQ (Single Correct Answer)
+2
-0.6
The digital circuit shown in the figure works as a GATE EE 2005 Digital Electronics - Sequential Circuits Question 16 English
A
$$JK$$ flip-flop
B
Clocked $$RS$$ flip-flop
C
$$T$$ flip-flop
D
Ring counter
4
GATE EE 2005
MCQ (Single Correct Answer)
+2
-0.6
Select the circuit which will produce the given output $$Q$$ for the input signals $${X_1}$$ and $${X_2}$$ given in the figure. GATE EE 2005 Digital Electronics - Sequential Circuits Question 15 English
A
GATE EE 2005 Digital Electronics - Sequential Circuits Question 15 English Option 1
B
GATE EE 2005 Digital Electronics - Sequential Circuits Question 15 English Option 2
C
GATE EE 2005 Digital Electronics - Sequential Circuits Question 15 English Option 3
D
GATE EE 2005 Digital Electronics - Sequential Circuits Question 15 English Option 4
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