The state transition diagram for the logic circuit shown is

A two-bit counter circuit is shown below

It the state $${Q_A}{Q_B}$$ of the counter at the clock time $${t_n}$$ is $$'10'$$ then the state $${Q_A}{Q_B}$$ of the counter at $${t_n} + 3$$ (after three clock cycles) will be

Select the circuit which will produce the given output $$Q$$ for the input signals $${X_1}$$ and $${X_2}$$ given in the figure.

The digital circuit shown in the figure works as a