A two-bit counter circuit is shown below

It the state $${Q_A}{Q_B}$$ of the counter at the clock time $${t_n}$$ is $$'10'$$ then the state $${Q_A}{Q_B}$$ of the counter at $${t_n} + 3$$ (after three clock cycles) will be

The digital circuit shown in the figure works as a

Select the circuit which will produce the given output $$Q$$ for the input signals $${X_1}$$ and $${X_2}$$ given in the figure.

The shift register shown in Fig. is initially loaded with the bit pattern $$1010.$$ Subsequently the shift register is clocked, and with each clock pulse the pattern gets shifted by one bit position to the right. With each shift, the bit at the serial input is pushed to the left most position $$(MSB).$$ After how many clock pulses will the content of the shift register become $$1010$$ again?