Combinational Circuits · Digital Electronics · GATE EE

Marks 1

To obtain the Boolean function $F(X, Y) = X\overline{Y} + \overline{X}$, the inputs $PQRS$ in the figure should be

GATE EE 2024

Consider the following circuit which uses a $$2$$-to-$$1$$ multiplexer as shown in the figure below. The Boolean expression for output $$F$$ in terms of $$A$$ and $$B$$ is

GATE EE 2016 Set 1

In the $$4 \times 1$$ multiplexer, the output $$F$$ is given by $$F = A \oplus B.$$ Find the required input $${{\rm I}_3}{{\rm I}_2}{{\rm I}_1}{{\rm I}_0}.$$

GATE EE 2015 Set 1

The output $$Y$$ of a $$2$$ $$-$$ bit comparator is logic $$1$$ whenever the $$2$$-bit input $$A$$ is greater than the $$2$$-bit input $$B.$$ The number of combination for which the output is logic $$1$$, is

GATE EE 2012

The output $$Y$$ of the logic circuit given below is

GATE EE 2011

Figure shows a $$4$$ to $$1$$ $$MUX$$ to be used to implement the sum $$S$$ of a $$1$$-bit full adder with input bits $$P$$ and $$Q$$ and the carry input $${C_{in}}.$$ Which of the following combinations of inputs to $${{\rm I}_0},\,\,{{\rm I}_1},\,\,{{\rm I}_2}$$ and $$\,\,{{\rm I}_3}$$ of the $$MUX$$ will realize the sum $$S$$?

GATE EE 2003

The output $$f$$ of the $$4$$- to- $$1$$ $$MUX$$ shown in fig. is

GATE EE 2001

Marks 2

A Boolean function $$f\left( {A,B,C,D} \right) = \Pi \left( {1,5,12,15} \right)$$ is to be implemented using an $$8 \times 1$$ multiplexer ($$A$$ is $$MSB$$). The inputs $$ABC$$ are connected to the select inputs $${S_2}{S_1}{S_0}$$ of the multiplexer respectively.

Which one of the following options gives the correct inputs to pins $$0,1,2,3,4,5,6,7$$ in order?

GATE EE 2015 Set 2

Two monoshot multivibrators, one positive edge triggered $$\left( {{M_1}} \right)$$ and another negative edge triggered $$\left( {{M_2}} \right)$$ are connected as shown in figure.

The monoshots $${{M_1}}$$ and $${{M_2}}$$ when triggered produce pulses of width $${{T_1}}$$ and $${{T_2}}$$ respectively, where $${T_1} > {T_2}.$$ The steady state output voltage $${V_0}$$ of the circuit is

GATE EE 2014 Set 3

A $$3$$-bit gray counter is used to control the output of the multiplexer as shown in the figure. The initial state of the counter is $${000_2}.$$ The output is pulled high. The output of the circuit follows the sequence

GATE EE 2014 Set 3

A $$3$$ line to $$8$$ line decoder, with active low outputs, is used to implement a $$3$$- variable Boolean function as shown in the figure: The simplified form of Boolean function $$F(X,Y,Z)$$ implemented in 'Product of Sum' form will be

GATE EE 2008

A $$4 \times 1\,\,MUX$$ is used to implement a $$3$$- input Boolean function as shown in figure. The Boolean function $$F\left( {A,\,\,B,\,\,C} \right)$$ implemented is

GATE EE 2006

The minimal product-of-sums function described by the $$K$$-map given in Fig.

GATE EE 2000

The logic function $$F = AC + ABD + ACD$$ is to be realized using an $$8$$ to $$1$$ multiplexer shown in figure, using $$A, C$$ and $$D$$ as control inputs.

$$(a)$$ Indicate the inputs to be applied at the terminals $$0$$ to $$7.$$
$$(b)$$ Can the function be realize using a $$4$$ to $$1$$ multiplexer?
State YES or NO.

GATE EE 1999

Match the following

GATE EE 1998

Marks 5

In a digital combinational circuit with $$4$$ inputs $$(A, B, C, D),$$ it is required to obtain an output of logical $$1$$ only for the input combination

$$(A = 1; B = C = D = 0).$$ It is known that the following combinations of input are forbidden:

$$ABCD = 1010, 1011, 1100, 1101, 1110, 1111$$
Evaluate the logical expression for the output and realize the same with two input $$NAND$$ gates. Assume that complements of inputs are not available.

GATE EE 1998

A $$3$$-input $$2$$-output priority encoder has the following truth table where $$'X'$$ indicate don't care conditions. Realize the logic using $$NAND$$ gates and inverters.

GATE EE 1997