The clock frequency applied to the digital circuit shown in the figure below is $$1$$ $$kHz.$$ If the initial state of the output $$Q$$ of the flip-flop is $$‘0’,$$ then the frequency of the output waveform $$Q$$ in $$kHz$$ is

The state transition diagram for the logic circuit shown is

A two-bit counter circuit is shown below

It the state $${Q_A}{Q_B}$$ of the counter at the clock time $${t_n}$$ is $$'10'$$ then the state $${Q_A}{Q_B}$$ of the counter at $${t_n} + 3$$ (after three clock cycles) will be

The digital circuit shown in the figure works as a