1
GATE EE 2021
MCQ (Single Correct Answer)
+2
-0.67
A counter is constructed with three D flip-flops. The input-output pairs are named as $\left(D_0, Q_0\right)$, $\left(D_1, Q_1\right)$ and $\left(D_2, Q_2\right)$, where the subscript 0 denotes LSB. The output sequence is desired to be Graycode sequence $000,001,011,010,110,111,101$ and 100 , repeating periodically. Note that the bits are listed in the $Q_2 Q_1 Q_0$ format. The combination logic expression for $D_1$ is
2
GATE EE 2017 Set 2
Numerical
+2
-0
For the synchronous sequential circuit shown below, the output $$Z$$ is zero for the initial conditions $${Q_A}{Q_B}{Q_C} = Q{'_A}Q{'_B}Q{'_C} = 100.$$
The minimum number if clock cycles after which the output $$Z$$ would again become zero is _____________.
Your input ____
3
GATE EE 2016 Set 1
MCQ (Single Correct Answer)
+2
-0.6
The current state $${Q_A}{Q_B}$$ of a two $$JK$$ flip-flop system is $$00.$$ Assume that the clock rise-time is much smaller than the delay of the $$JK$$ flip-flop. The next state of the system is
4
GATE EE 2015 Set 1
Numerical
+2
-0
The figure shows a digital circuit constructed using negative edge triggered $$J-K$$ flip flops. Assume a starting state of $${Q_2}\,{Q_1}\,{Q_0} = 000.$$ This state $${Q_2}\,{Q_1}\,{Q_0} = 000$$ will repeat after _____ number of cycles of the clock $$CLK.$$
Your input ____
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