1
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
For the circuit shown, the counter state (Q1 Q0) follows the sequence GATE ECE 2007 Digital Circuits - Sequential Circuits Question 35 English
A
00,01,10,11,00......
B
00,01,10,00,01.......
C
00,01,11,00,01.....
D
00,10,11,00,10......
2
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
The circuit diagram of a standard TTL NOT gate is shown in the figure. When $${V_i}$$= 2.5V, the modes of operation of the transistors will be: GATE ECE 2007 Digital Circuits - Logic Families Question 2 English
A

$${Q_1}$$ :reverse active

$${Q_2}$$; normal active

$${Q_3}$$; :saturation;

$${Q_4}$$ :cut-off

B

$${Q_1}$$ :reverse active

$${Q_2}$$: saturation

$${Q_3}$$: saturation

$${Q_4}$$ : cut-off

C

$${Q_1}$$ : normal active

$${Q_2}$$; cut-off

$${Q_3}$$; cut-off

$${Q_4}$$ : saturation

D

$${Q_1}$$ : :saturation

$${Q_2}$$: :saturation

$${Q_3}$$ :saturation

$${Q_4}$$ : normal active

3
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: X=0, Y=1; X=0, Y=0; X=1, Y=1. The corresponding stable P, Q outputs will be GATE ECE 2007 Digital Circuits - Sequential Circuits Question 26 English
A
P = 1, Q = 0; P = 1, Q = 0; P = 1, Q = 0 or P = 0, Q = 1
B
P = 1, Q = 0; P = 0, Q = 1; or P = 0, Q = 1; P = 0, Q = 1
C
P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 0 or P = 0, Q = 1
D
P = 1, Q = 0; P = 1, Q = 1; P = 1, Q = 1
4
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
In the digital-to-Analog converter circuit shown in the figure below,
$${V_{R\,}}\, = \,10V$$ and $$R\, = \,10k\Omega $$ GATE ECE 2007 Digital Circuits - Analog to Digital and Digital to Analog Converters Question 5 English

The current i is

A
$$31.25\,\mu {\rm A}$$
B
$$62.5\,\mu {\rm A}$$
C
$$125\,\mu {\rm A}$$
D
$$250\,\mu {\rm A}$$
EXAM MAP
Medical
NEET
Graduate Aptitude Test in Engineering
GATE CSEGATE ECEGATE EEGATE MEGATE CEGATE PIGATE IN
CBSE
Class 12