1
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
Consider a linear system whose state space Representation is $$\mathop x\limits^ \bullet \left( t \right) = AX\left( t \right).$$
If the initial state vector of the system is $$x\left( 0 \right) = \left[ {\matrix{ 1 \cr { - 2} \cr } } \right],$$
then the system response is $$x\left( t \right) = \left[ {\matrix{ {{e^{ - 2t}}} \cr { - 2{e^{ - 2t}}} \cr } } \right].$$
If the initial state vector of the system changes to $$x\left( 0 \right) = \left[ {\matrix{ 1 \cr { - 1} \cr } } \right],$$
then the system response becomes $$x\left( t \right) = \left[ {\matrix{ {{e^{ - t}}} \cr { - {e^{ - t}}} \cr } } \right].$$

The system matrix a is

A
$$\left[ {\matrix{ 0 & 1 \cr { - 1} & 1 \cr } } \right]$$
B
$$\left[ {\matrix{ 1 & 1 \cr { - 1} & { - 2} \cr } } \right]$$
C
$$\left[ {\matrix{ 2 & 1 \cr { - 1} & { - 1} \cr } } \right]$$
D
$$\left[ {\matrix{ 0 & 1 \cr { - 2} & { - 3} \cr } } \right]$$
2
GATE ECE 2007
MCQ (Single Correct Answer)
+2
-0.6
The state space representation of a separately excited DC servo motor dynamics is given as $$$\left[ {\matrix{ {{{d\omega } \over {dt}}} \cr {{{d{i_a}} \over {dt}}} \cr } } \right] = \left[ {\matrix{ { - 1} & 1 \cr { - 1} & { - 10} \cr } } \right]\left[ {\matrix{ \omega \cr {{i_a}} \cr } } \right] + \left[ {\matrix{ 0 \cr {10} \cr } } \right]u.$$$

Where 'ω' is the speed of the motor, 'ia' is the armature current and u is the armature voltage. The transfer function $${{\omega \left( s \right)} \over {U\left( s \right)}}$$ of the motor is

A
$${{10} \over {{s^2} + 11s + 11}}$$
B
$${1 \over {{s^2} + 11s + 11}}$$
C
$${{10s + 10} \over {{s^2} + 11s + 11}}$$
D
$${1 \over {{s^2} + s + 11}}$$
3
GATE ECE 2007
MCQ (Single Correct Answer)
+1
-0.3
X = 01110 and Y = 11001 are two 5-bit binary numbers represented in two’s complement format. The sum of X and Y represented in two’s complement format using 6 bits is:
A
100111
B
001000
C
000111
D
101001
4
GATE ECE 2007
MCQ (Single Correct Answer)
+1
-0.3
The Boolean function Y=AB+CD is to be realized using only 2-input NAND gates. The minimum number of gates required is
A
2
B
3
C
4
D
5
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