GATE CSE 2013 | Memory Interfacing Question 28 | Computer Organization

GATE CSE 2013

MCQ (Single Correct Answer)

-0.3

In a $$k$$-way set associative cache, the cache is divided into $$v$$ sets, each of which consists of $$k$$ lines. The lines of a set are placed in sequence one after another. The lines in set $$s$$ are sequenced before the lines in set $$(s+1).$$ The main memory blocks are numbered $$0$$ onwards. The main memory block numbered $$j$$ must be mapped to any one of the cache lines from

$${\left( {j\,\,\bmod \,\,v} \right)^ * }k\,\,$$ to $${\left( {j\,\,\bmod \,\,v} \right)^ * }k\, + \,\,\,\,\,\,\left( {k - 1} \right)$$

$${\left( {j\,\,\bmod \,\,v} \right)}\,\,$$ to $$\left( {j\,\,\bmod \,\,v} \right)\, + \,\left( {k - 1} \right)$$

$${\left( {j\,\,\bmod \,\,k} \right) }\,\,$$ to $$\left( {j\,\,\bmod \,\,k} \right)\, + \,\left( {v - 1} \right)$$

$${\left( {j\,\,\bmod \,\,k} \right)^ * }v\,\,$$ to $${\left( {j\,\,\bmod \,\,k} \right)^ * }\,v + \,\left( {v - 1} \right)$$

GATE CSE 2012

MCQ (Single Correct Answer)

-0.3

The amount of $$ROM$$ needed to implement a $$4$$ bit multiplier is

$$64$$ bits

$$128$$ bits

$$1$$ $$K$$bits

$$2$$ $$K$$bits

GATE CSE 2010

MCQ (Single Correct Answer)

-0.3

A main memory unit with a capacity of $$4$$ megabytes is built using $$1M \times 1$$-bit $$DRAM$$ chips. Each $$DRAM$$ chip has $$1K$$ rows of cells with $$1K$$ cells in each row. The time taken for a single refresh operation is $$100$$ nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is

$$100$$ nanoseconds

$$100 * {2^{10}}$$ nanoseconds

$$100 * {2^{20}}$$ nanoseconds

$$3200 * {2^{20}}$$ nanoseconds

GATE CSE 2009

MCQ (Single Correct Answer)

-0.3

How many $$32k$$ x $$1$$ $$RAM$$ chips are needed to provide a memory capacity of $$256$$ $$K$$-bytes?

$$8$$

$$32$$

$$64$$

$$128$$