1
GATE CSE 2019
+1
-0.33
A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields resectively in the addresses generated by the processor?
A
28 bits and 4 bits
B
24 bits and 4 bits
C
24 bits and 0 bits
D
28 bits and 0 bits
2
GATE CSE 2018
Numerical
+1
-0
A $$32$$-bit wide main memory unit with a capacity of $$1$$ $$GB$$ is built using $$256M\,\, \times \,\,4$$-bit $$DRAM$$ chips. The number of rows of memory cells in the $$DRAM$$ chip is $${2^{14}}.$$ The time taken to perform one refresh operation is $$50$$ nanoseconds. The refresh period is $$2$$ milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is __________.
3
GATE CSE 2016 Set 1
Numerical
+1
-0
A processor can support a maximum memory of $$4$$ $$GB,$$ where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ___________ bits.
4
GATE CSE 2015 Set 3
+1
-0.3
Consider a machine with a byte addressable main memory of $${2^{20}}$$ bytes, block size of $$16$$ bytes and a direct mapped cache having $${2^{12}}$$ cache lines. Let the addresses of two consecutive bytes in main memory be $${\left( {E201F} \right)_{16}}$$ and $${\left( {E2020} \right)_{16}}$$. What are the tag and cache line address (in $$hex$$) for main memory address $${\left( {E201F} \right)_{16}}$$?
A
$$E, 201$$
B
$$F, 201$$
C
$$E, E20$$
D
$$2, 01F$$
GATE CSE Subjects
Discrete Mathematics
Programming Languages
Theory of Computation
Operating Systems
Digital Logic
Computer Organization
Database Management System
Data Structures
Computer Networks
Algorithms
Compiler Design
Software Engineering
Web Technologies
General Aptitude
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