1
GATE CSE 2015 Set 3
MCQ (Single Correct Answer)
+1
-0.3
Consider a machine with a byte addressable main memory of $${2^{20}}$$ bytes, block size of $$16$$ bytes and a direct mapped cache having $${2^{12}}$$ cache lines. Let the addresses of two consecutive bytes in main memory be $${\left( {E201F} \right)_{16}}$$ and $${\left( {E2020} \right)_{16}}$$. What are the tag and cache line address (in $$hex$$) for main memory address $${\left( {E201F} \right)_{16}}$$?
A
$$E, 201$$
B
$$F, 201$$
C
$$E, E20$$
D
$$2, 01F$$
2
GATE CSE 2014 Set 1
MCQ (Single Correct Answer)
+1
-0.3
An access sequence of cache block addresses is of length $$N$$ and contains $$n$$ unique block address. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $$k.$$ What is the miss ratio if the access sequence is passed through a cache of associativity $$A\, \ge \,k$$ exercising least-recently-used replacement policy?
A
$$n/N$$
B
$$1/N$$
C
$$1/A$$
D
$$k/n$$
3
GATE CSE 2013
MCQ (Single Correct Answer)
+1
-0.3
In a $$k$$-way set associative cache, the cache is divided into $$v$$ sets, each of which consists of $$k$$ lines. The lines of a set are placed in sequence one after another. The lines in set $$s$$ are sequenced before the lines in set $$(s+1).$$ The main memory blocks are numbered $$0$$ onwards. The main memory block numbered $$j$$ must be mapped to any one of the cache lines from
A
$${\left( {j\,\,\bmod \,\,v} \right)^ * }k\,\,$$ to $${\left( {j\,\,\bmod \,\,v} \right)^ * }k\, + \,\,\,\,\,\,\left( {k - 1} \right)$$
B
$${\left( {j\,\,\bmod \,\,v} \right)}\,\,$$ to $$\left( {j\,\,\bmod \,\,v} \right)\, + \,\left( {k - 1} \right)$$
C
$${\left( {j\,\,\bmod \,\,k} \right) }\,\,$$ to $$\left( {j\,\,\bmod \,\,k} \right)\, + \,\left( {v - 1} \right)$$
D
$${\left( {j\,\,\bmod \,\,k} \right)^ * }v\,\,$$ to $${\left( {j\,\,\bmod \,\,k} \right)^ * }\,v + \,\left( {v - 1} \right)$$
4
GATE CSE 2012
MCQ (Single Correct Answer)
+1
-0.3
The amount of $$ROM$$ needed to implement a $$4$$ bit multiplier is
A
$$64$$ bits
B
$$128$$ bits
C
$$1$$ $$K$$bits
D
$$2$$ $$K$$bits
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