Consider the following processor design characteristics.

$$\,\,\,\,\,\,\,{\rm I}.\,\,\,\,\,$$ Register-to-register arithmetic operations only
$$\,\,\,\,\,{\rm I}{\rm I}.\,\,\,\,\,$$ Fixed-length instruction format
$$\,\,\,{\rm I}{\rm I}{\rm I}.\,\,\,\,\,$$ Hardwired control unit

Which of the characteristics above are used in the design of a $$RISC$$ processor?

The size of the data count register of a $$DMA$$ controller is $$16$$ bits. The processor needs to transfer a file of $$29,154$$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $$DMA$$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ___________.

Consider the following sequence of micro-operations
$$\eqalign{ & \,\,\,\,\,\,\,\,\,\,\,\,\,MBR\,\,\,\,\,\,\, \leftarrow PC \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,MAR\,\,\,\,\,\,\, \leftarrow X \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,PC\,\,\,\,\,\,\,\,\,\,\,\, \leftarrow Y \cr & \,\,\,\,\,\,\,\,\,\,\,\,\,Memory\, \leftarrow MBR \cr} $$

Which one of the following is a possible operation performed by this sequence?

Consider the following data path of a $$CPU$$

The, $$ALU$$, the bus and all the registers in the data path are of identical size. All operations including incrementation of the $$PC$$ and the $$GPRs$$ are to be carried out in the $$ALU.$$ Two clock cycle are needed for memory read operation-the first one for loading address in the $$MAR$$ and the next one for loading data from the memory but into the $$MDR.$$

The instruction $$''call$$ $$Rn,sub''$$ is a two word instruction. Assuming that $$PC$$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is $$$\eqalign{ & Rn < = PC + 1; \cr & PC < = M\left[ {PC} \right]; \cr} $$$
The minimum number of $$CPU$$ clock cycles needed during the execution cycle of this instruction is :