1
GATE CSE 2016 Set 1
Numerical
+1
-0
A processor can support a maximum memory of $$4$$ $$GB,$$ where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least ___________ bits.
2
GATE CSE 2015 Set 3
+1
-0.3
Consider a machine with a byte addressable main memory of $${2^{20}}$$ bytes, block size of $$16$$ bytes and a direct mapped cache having $${2^{12}}$$ cache lines. Let the addresses of two consecutive bytes in main memory be $${\left( {E201F} \right)_{16}}$$ and $${\left( {E2020} \right)_{16}}$$. What are the tag and cache line address (in $$hex$$) for main memory address $${\left( {E201F} \right)_{16}}$$?
A
$$E, 201$$
B
$$F, 201$$
C
$$E, E20$$
D
$$2, 01F$$
3
GATE CSE 2015 Set 2
Numerical
+1
-0
Assume that for a certain processor, a read request takes $$50$$ nanoseconds on a cache miss and $$5$$ nanoseconds on a cache hit. Suppose while running a program, it was observed that $$80\%$$ of the processor's read requests result in a cache hit. The average read access time in nanoseconds is __________.
4
GATE CSE 2014 Set 1
+1
-0.3
An access sequence of cache block addresses is of length $$N$$ and contains $$n$$ unique block address. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $$k.$$ What is the miss ratio if the access sequence is passed through a cache of associativity $$A\, \ge \,k$$ exercising least-recently-used replacement policy?
A
$$n/N$$
B
$$1/N$$
C
$$1/A$$
D
$$k/n$$
GATE CSE Subjects
EXAM MAP
Medical
NEET