GATE CSE 2022 | Memory Interfacing Question 5 | Computer Organization

GATE CSE 2022

MCQ (More than One Correct Answer)

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Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?

Each cache block in WB and WT has a dirty bit.

Every write hit in WB leads to a data transfer from cache to main memory.

Eviction of a block from WT will not lead to data transfer from cache to main memory.

A read miss in WB will never lead to eviction of a dirty block from WB.

GATE CSE 2021 Set 2

Numerical

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Consider a set-associative cache of size 2 KB (1 KB = 2¹⁰bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is _______

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GATE CSE 2021 Set 1

Numerical

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Consider a computer system with a byte-addressable primary memory of size 2³² bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB = 2¹⁰ bytes), and each cache block is of size 64 bytes.

The size of the tag field is ______ bits.

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GATE CSE 2020

Numerical

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A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is _____.

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