1
GATE CSE 2010
MCQ (Single Correct Answer)
+1
-0.3
A main memory unit with a capacity of $$4$$ megabytes is built using $$1M \times 1$$-bit $$DRAM$$ chips. Each $$DRAM$$ chip has $$1K$$ rows of cells with $$1K$$ cells in each row. The time taken for a single refresh operation is $$100$$ nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is
2
GATE CSE 2009
MCQ (Single Correct Answer)
+1
-0.3
How many $$32k$$ x $$1$$ $$RAM$$ chips are needed to provide a memory capacity of $$256$$ $$K$$-bytes?
3
GATE CSE 2007
MCQ (Single Correct Answer)
+1
-0.3
Consider a $$4$$-way set associative cache consisting of $$128$$ lines with a line size of $$64$$ words. The $$CPU$$ generates a $$20$$-bit address of a word in main memory. The numbers of bits in the TAG, LINE and WORD fields are respectively
4
GATE CSE 2005
MCQ (Single Correct Answer)
+1
-0.3
Increasing the $$RAM$$ of a computer typically improves performance because
Questions Asked from Memory Interfacing (Marks 1)
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GATE CSE Subjects
Theory of Computation
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Algorithms
Database Management System
Data Structures
Computer Networks
Software Engineering
Compiler Design
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Discrete Mathematics
Programming Languages