1
GATE CSE 2015 Set 2
Numerical
+1
-0
Assume that for a certain processor, a read request takes $$50$$ nanoseconds on a cache miss and $$5$$ nanoseconds on a cache hit. Suppose while running a program, it was observed that $$80\% $$ of the processor's read requests result in a cache hit. The average read access time in nanoseconds is __________.
Your input ____
2
GATE CSE 2014 Set 1
MCQ (Single Correct Answer)
+1
-0.3
An access sequence of cache block addresses is of length $$N$$ and contains $$n$$ unique block address. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $$k.$$ What is the miss ratio if the access sequence is passed through a cache of associativity $$A\, \ge \,k$$ exercising least-recently-used replacement policy?
3
GATE CSE 2013
MCQ (Single Correct Answer)
+1
-0.3
In a $$k$$-way set associative cache, the cache is divided into $$v$$ sets, each of which consists of $$k$$ lines. The lines of a set are placed in sequence one after another. The lines in set $$s$$ are sequenced before the lines in set $$(s+1).$$ The main memory blocks are numbered $$0$$ onwards. The main memory block numbered $$j$$ must be mapped to any one of the cache lines from
4
GATE CSE 2012
MCQ (Single Correct Answer)
+1
-0.3
The amount of $$ROM$$ needed to implement a $$4$$ bit multiplier is
Questions Asked from Memory Interfacing (Marks 1)
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GATE CSE Subjects
Theory of Computation
Operating Systems
Algorithms
Database Management System
Data Structures
Computer Networks
Software Engineering
Compiler Design
Web Technologies
General Aptitude
Discrete Mathematics
Programming Languages