1
GATE CSE 2021 Set 1
Numerical
+1
-0
Consider a computer system with a byte-addressable primary memory of size 232 bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB = 210 bytes), and each cache block is of size 64 bytes.
The size of the tag field is ______ bits.
Your input ____
2
GATE CSE 2020
Numerical
+1
-0
A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is _____.
Your input ____
3
GATE CSE 2019
MCQ (Single Correct Answer)
+1
-0.33
A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields resectively in the addresses generated by the processor?
4
GATE CSE 2019
MCQ (Single Correct Answer)
+1
-0.33
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?
Questions Asked from Memory Interfacing (Marks 1)
Number in Brackets after Paper Indicates No. of Questions
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GATE CSE Subjects
Theory of Computation
Operating Systems
Algorithms
Database Management System
Data Structures
Computer Networks
Software Engineering
Compiler Design
Web Technologies
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Discrete Mathematics
Programming Languages