1
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
Consider a direct mapped cache of size $$32$$ $$KB$$ with block size $$32$$ bytes. The $$CPU$$ generates $$32$$ bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively
A
$$10, 17$$
B
$$10,22$$
C
$$15,17$$
D
$$5, 17$$
2
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, uses the least recently used $$(LRU)$$ scheme. The number of cache misses for the following sequence of blocks addresses is $$8,12,0,12,8$$
A
$$2$$
B
$$3$$
C
$$4$$
D
$$5$$
3
GATE CSE 1990
Subjective
+2
-0
A block -set associative cache memory consists of $$128$$ blocks divided into four block sets. The main memory consists of $$16,384$$ blocks and each blocks contains $$256$$ eight bit words.

(i) How many bits are required for addressing the main memory?

(ii) How many bits are needed to represent the TAG, SET and WORD fields?

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