Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words $\mathrm{P}, \mathrm{Q}, \mathrm{R}$, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence $\mathrm{P}, \mathrm{Q}, \mathrm{R}, \mathrm{S}, \mathrm{P}, \mathrm{Q}, \mathrm{R}, \mathrm{S}, \ldots$

Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word $=1$ byte).

P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32

Which of the following statements is/are true?

Note: $1 \mathrm{~K}=2^{10}$ and $1 \mathrm{M}=2^{20}$

Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0 . The word with physical address 0xA2C28 is mapped to the cache block number $176_{10}$. The maximum possible size of the cache (in KB ) for this configuration is $\_\_\_\_$ . (answer in integer)

Note: $1 \mathrm{~K}=2^{10}$ and $1 \mathrm{M}=2^{20}$

The size of the physical address space of a processor is $2^{32}$ bytes. The capacity of a cache memory unit is $2^{23}$ bytes. The cache block size is 128 bytes. The cache memory unit can be built as a direct mapped cache or as a $K$-way set-associative cache, where $K=2^L$ and $L \in\{1,2,3\}$. Let the length of the TAG field be $M$ bits for the direct mapped cache, and $N$ bits for the set-associative cache.

Which one of the following options is true?

For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block. Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?