1
GATE CSE 2021 Set 2
MCQ (Single Correct Answer)
+2
-0.66

Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

S1 : Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2.

S2 : Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct? 

A
S1 is true and S2 is true
B
S1 is false and S2 is true
C
S1 is false and S2 is false
D
S1 is true and S2 is false
2
GATE CSE 2020
MCQ (Single Correct Answer)
+2
-0.67
A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.

A1 = 0x42C8A4, A2 = 0x546888, A3 = 0x6A289C, A4 = 0x5E4880

Which one of the following is TRUE?
A
A1 and A4 are mapped to different cache sets.
B
A1 and A3 are mapped to the same cache set.
C
A3 and A4 are mapped to the same cache set.
D
A2 and A3 are mapped to the same cache set.
3
GATE CSE 2019
Numerical
+2
-0
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a $60-\mathrm{MHz}$ clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is _________ $\times 10^6$ bytes $/ \mathrm{sec}$.
Your input ____
4
GATE CSE 2018
MCQ (Single Correct Answer)
+2
-0.6
The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capacity of cache memory is $${2^N}$$ bytes. The size of each cache block is $${2^M}$$ words. For a $$K$$-way set-associative cache memory, the length (in number of bits) of the tag field is
A
$$P - N - lo{g_2}K$$
B
$$P - N + lo{g_2}K$$
C
$$P - N - M - W - lo{g_2}\,\,K$$
D
$$P - N - M - W + lo{g_2}\,\,K$$
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