1
GATE CSE 2019
Numerical
+2
-0
A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a $60-\mathrm{MHz}$ clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is _________ $\times 10^6$ bytes $/ \mathrm{sec}$.
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2
GATE CSE 2018
MCQ (Single Correct Answer)
+2
-0.6
The size of the physical address space of a processor is $${2^P}$$ bytes. The word length is $${2^W}$$ bytes. The capacity of cache memory is $${2^N}$$ bytes. The size of each cache block is $${2^M}$$ words. For a $$K$$-way set-associative cache memory, the length (in number of bits) of the tag field is
A
$$P - N - lo{g_2}K$$
B
$$P - N + lo{g_2}K$$
C
$$P - N - M - W - lo{g_2}\,\,K$$
D
$$P - N - M - W + lo{g_2}\,\,K$$
3
GATE CSE 2016 Set 2
Numerical
+2
-0
The width of the physical address on a machine is $$40$$ bits. The width of the tag field in a $$512$$ $$KB$$ $$8$$-way set associative cache is _____________ bits.
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4
GATE CSE 2016 Set 2
Numerical
+2
-0
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $$1$$ $$ms$$ and to read a block from the disk is $$10$$ $$ms.$$ Assume that the cost of checking whether a block exists in the cache is negligible. Available cache sizes are in multiples of $$10$$ $$MB.$$ GATE CSE 2016 Set 2 Computer Organization - Memory Interfacing Question 21 English

The smallest cache size required to ensure an average read latency of less than $$6$$ $$ms$$ is _________ $$MB.$$

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GATE CSE Subjects
Software Engineering
Web Technologies
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