For inclusion to hold between two cache levels $$L1$$ and $$L2$$ in a multilevel cache hierarchy, which of the following are necessary?

$$1.$$ $$L1$$ must be a write-through cache
$$2.$$ $$L2$$ must be a write-through cache
$$3.$$ The associativity of $$L2$$ must be greater than that of $$L1$$
$$4.$$ The $$L2$$ cache must be at least as large as the $$L1$$ cache

Consider a machine with a byte addressable main memory of $${2^{16}}$$ bytes. Assume that a direct mapped data cache consisting of $$32$$ lines of $$64$$ bytes each is used in the system. $$A\,\,50 \times 50$$ two-dimensional array of bytes is stored in the main memory starting from memory location $$1100H.$$ Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses.

How many data cache misses will occur in total?

Consider a machine with a byte addressable main memory of $${2^{16}}$$ bytes. Assume that a direct mapped data cache consisting of $$32$$ lines of $$64$$ bytes each is used in the system. $$A\,\,50 \times 50$$ two-dimensional array of bytes is stored in the main memory starting from memory location $$1100H.$$ Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses.

Which of the following lines of the data cache will be replaced by new blocks in accessing the array?

Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same size but direct mapped. The size of an address is $$32$$ bits in both cases. $$A$$ $$2$$-to-$$1$$ multiplexer has latency. of $$0.6$$ $$ns$$ while a $$k$$-bit comparator has a latency of $$k/10$$ $$ns.$$ The bit latency of the set associative organization is $${h_1}$$ while that of the direct mapped one is $${h_2}.$$

The value of $${h_1}$$ is