1
GATE CSE 2022
MCQ (More than One Correct Answer)
+1
-0.33

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS .....). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0$$\times$$A248, 0$$\times$$C28A, 0$$\times$$CA8A, and 0$$\times$$A262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

A
Every access to S is a hit.
B
Once P is brought to the cache it is never evicted.
C
At the end of the execution only R and S reside in the cache.
D
Every access to R evicts Q from the cache.
2
GATE CSE 2021 Set 2
Numerical
+1
-0
Consider a set-associative cache of size 2 KB (1 KB = 210 bytes) with cache block size of 64 bytes. Assume that the cache is byte-addressable and a 32-bit address is used for accessing the cache. If the width of the tag field is 22 bits, the associativity of the cache is _______
Your input ____
3
GATE CSE 2020
Numerical
+1
-0.33
A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is _____.
Your input ____
4
GATE CSE 2019
MCQ (Single Correct Answer)
+1
-0.33
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? GATE CSE 2019 Computer Organization - Memory Interfacing Question 9 English
A
C800 to CFFF
B
C800 to C8FF
C
DA00 to DFFF
D
CA00 to CAFF
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