1
GATE CSE 2024 Set 1
MCQ (More than One Correct Answer)
+2
-0.66

Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?

A

A read miss in WBC never evicts a dirty block

B

A read miss in WTC never triggers a write back operation of a cache block to main memory

C

A write hit in WBC can modify the value of the dirty bit of a cache block

D

A write miss in WTC always writes the victim cache block to main memory before loading the missed block to the cache

2
GATE CSE 2024 Set 1
Numerical
+2
-0.66

A given program has 25% load/store instructions. Suppose the ideal CPI (cycles per instruction) without any memory stalls is 2. The program exhibits 2% miss rate on instruction cache and 8% miss rate on data cache. The miss penalty is 100 cycles. The speedup (rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is ______

Your input ____
3
GATE CSE 2023
Numerical
+2
-0.67

An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET.

The number of bits in the TAG is __________.

Your input ____
4
GATE CSE 2021 Set 1
Numerical
+2
-0.67

Consider a computer system with a byte-addressable primary memory of size 232 bytes. Assume the computer system has a direct-mapped cache of size 32 KB (1 KB = 210 bytes), and each cache block is of size 64 bytes.

The size of the tag field is ______ bits.

Your input ____
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