1
GATE CSE 2007
MCQ (Single Correct Answer)
+2
-0.6
Consider a machine with a byte addressable main memory of $${2^{16}}$$ bytes. Assume that a direct mapped data cache consisting of $$32$$ lines of $$64$$ bytes each is used in the system. $$A\,\,50 \times 50$$ two-dimensional array of bytes is stored in the main memory starting from memory location $$1100H.$$ Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses.

How many data cache misses will occur in total?

A
$$48$$
B
$$50$$
C
$$56$$
D
$$59$$
2
GATE CSE 2007
MCQ (Single Correct Answer)
+2
-0.6
Consider a machine with a byte addressable main memory of $${2^{16}}$$ bytes. Assume that a direct mapped data cache consisting of $$32$$ lines of $$64$$ bytes each is used in the system. $$A\,\,50 \times 50$$ two-dimensional array of bytes is stored in the main memory starting from memory location $$1100H.$$ Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses.

Which of the following lines of the data cache will be replaced by new blocks in accessing the array?

A
line $$4$$ to line $$11$$
B
line $$4$$ to line $$12$$
C
line $$0$$ to line $$7$$
D
line $$0$$ to line $$8$$
3
GATE CSE 2006
MCQ (Single Correct Answer)
+2
-0.6
Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same size but direct mapped. The size of an address is $$32$$ bits in both cases. $$A$$ $$2$$-to-$$1$$ multiplexer has latency. of $$0.6$$ $$ns$$ while a $$k$$-bit comparator has a latency of $$k/10$$ $$ns.$$ The bit latency of the set associative organization is $${h_1}$$ while that of the direct mapped one is $${h_2}.$$

The value of $${h_1}$$ is

A
$$2.4$$ $$ns$$
B
$$2.3$$ $$ns$$
C
$$1.8$$ $$ns$$
D
$$1.7$$ $$ns$$
4
GATE CSE 2006
MCQ (Single Correct Answer)
+2
-0.6
A $$CPU$$ has a cache with block size $$64$$ bytes. The main memory has $$k$$ banks, each bank being $$c$$ bytes wide. Consecutive $$c$$-byte chunks are mapped on consecutive banks with wrap-around. All the $$k$$ banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the $$k$$ banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes $$k/2$$ $$ns.$$ The latency of one bank access is $$80$$ $$ns.$$ If $$c=2$$ and $$k=24,$$ then latency of retrieving a cache block starting at address zero from main memory is
A
$$92$$ $$ns$$
B
$$104$$ $$ns$$
C
$$172$$ $$ns$$
D
$$184$$ $$ns$$
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