1
GATE CSE 2010
MCQ (Single Correct Answer)
+2
-0.6
A computer system has an $$L1$$ cache, an $$L2$$ cache, and a main memory unit connected as shown below. The block size in $$L1$$ cache is $$4$$ words. The block size in $$L2$$ cache is $$16$$ words. The memory access times are $$2$$ nanoseconds, $$20$$ nanoseconds and $$200$$ nanoseconds for $$L1$$ cache, $$L2$$ cache and main memory unit respectively. GATE CSE 2010 Computer Organization - Memory Interfacing Question 20 English

When there is a miss in both $$L1$$ cache and $$L2$$ cache, first a block is transferred from main memory to $$L2$$ cache, and then a block is transferred from $$L2$$ cache to $$L1$$ cache.
What is the total time taken for these transfers?

A
$$222$$ nanoseconds
B
$$888$$ nanoseconds
C
$$902$$ nanoseconds
D
$$968$$ nanoseconds
2
GATE CSE 2010
MCQ (Single Correct Answer)
+2
-0.6
A computer system has an $$L1$$ cache, an $$L2$$ cache, and a main memory unit connected as shown below. The block size in $$L1$$ cache is $$4$$ words. The block size in $$L2$$ cache is $$16$$ words. The memory access times are $$2$$ nanoseconds, $$20$$ nanoseconds and $$200$$ nanoseconds for $$L1$$ cache, $$L2$$ cache and main memory unit respectively. GATE CSE 2010 Computer Organization - Memory Interfacing Question 21 English

When there is a miss in $$L1$$ cache and a hit in $$L2$$ cache, a block is transferred from $$L2$$ cache to $$L1$$ cache. What is the time taken for this transfer?

A
$$2$$ nanoseconds
B
$$20$$ nanoseconds
C
$$22$$ nanoseconds
D
$$88$$ nanoseconds
3
GATE CSE 2009
MCQ (Single Correct Answer)
+2
-0.6
Consider a $$4$$-way set associative cache (initially empty) with total $$16$$ cache blocks. The main memory consists of $$256$$ blocks and the request for memory blocks is in the following order:
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.

Which one of the following memory block will NOT be in cache if $$LRU$$ replacement policy is used?

A
$$3$$
B
$$8$$
C
$$129$$
D
$$216$$
4
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
For inclusion to hold between two cache levels $$L1$$ and $$L2$$ in a multilevel cache hierarchy, which of the following are necessary?

$$1.$$ $$L1$$ must be a write-through cache
$$2.$$ $$L2$$ must be a write-through cache
$$3.$$ The associativity of $$L2$$ must be greater than that of $$L1$$
$$4.$$ The $$L2$$ cache must be at least as large as the $$L1$$ cache

A
$$4$$ only
B
$$1$$ and $$2$$ only
C
$$1,2$$ and $$4$$ only
D
$$1,2,3$$ and $$4$$
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