1
GATE CSE 2006
MCQ (Single Correct Answer)
+2
-0.6
Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same size but direct mapped. The size of an address is $$32$$ bits in both cases. $$A$$ $$2$$-to-$$1$$ multiplexer has latency. of $$0.6$$ $$ns$$ while a $$k$$-bit comparator has a latency of $$k/10$$ $$ns.$$ The bit latency of the set associative organization is $${h_1}$$ while that of the direct mapped one is $${h_2}.$$

The value of $${h_1}$$ is

A
$$2.4$$ $$ns$$
B
$$2.3$$ $$ns$$
C
$$1.8$$ $$ns$$
D
$$1.7$$ $$ns$$
2
GATE CSE 2006
MCQ (Single Correct Answer)
+2
-0.6
Consider two cache organization: The first one is $$32$$ $$KB$$ $$2$$-way set associate with $$32$$-byte block size. The second one is of the same size but direct mapped. The size of an address is $$32$$ bits in both cases. $$A$$ $$2$$-to-$$1$$ multiplexer has latency. of $$0.6$$ $$ns$$ while a $$k$$-bit comparator has a latency of $$k/10$$ $$ns.$$ The bit latency of the set associative organization is $${h_1}$$ while that of the direct mapped one is $${h_2}.$$

The value of $${h_2}$$ is

A
$$2.4$$ $$ns$$
B
$$2.3$$ $$ns$$
C
$$1.8$$ $$ns$$
D
$$1.7$$ $$ns$$
3
GATE CSE 2005
MCQ (Single Correct Answer)
+2
-0.6
Consider a direct mapped cache of size $$32$$ $$KB$$ with block size $$32$$ bytes. The $$CPU$$ generates $$32$$ bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively
A
$$10, 17$$
B
$$10,22$$
C
$$15,17$$
D
$$5, 17$$
4
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, uses the least recently used $$(LRU)$$ scheme. The number of cache misses for the following sequence of blocks addresses is $$8,12,0,12,8$$
A
$$2$$
B
$$3$$
C
$$4$$
D
$$5$$
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