1
GATE CSE 2023
Numerical
+2
-0.67

An 8-way set associative cache of size 64 KB (1 KB = 1024 bytes) is used in a system with 32-bit address. The address is sub-divided into TAG, INDEX, and BLOCK OFFSET.

The number of bits in the TAG is __________.

Your input ____
2
GATE CSE 2022
MCQ (More than One Correct Answer)
+2
-0.67

Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS .....). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0$$\times$$A248, 0$$\times$$C28A, 0$$\times$$CA8A, and 0$$\times$$A262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?

A
Every access to S is a hit.
B
Once P is brought to the cache it is never evicted.
C
At the end of the execution only R and S reside in the cache.
D
Every access to R evicts Q from the cache.
3
GATE CSE 2021 Set 2
MCQ (Single Correct Answer)
+2
-0.66

Assume a two-level inclusive cache hierarchy, L1 and L2, where L2 is the larger of the two. Consider the following statements.

S1 : Read misses in a write through L1 cache do not result in writebacks of dirty lines to the L2.

S2 : Write allocate policy must be used in conjunction with write through caches and no-write allocate policy is used with writeback caches.

Which of the following statements is correct? 

A
S1 is true and S2 is true
B
S1 is false and S2 is true
C
S1 is false and S2 is false
D
S1 is true and S2 is false
4
GATE CSE 2020
MCQ (Single Correct Answer)
+2
-0.67
A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.

A1 = 0x42C8A4, A2 = 0x546888, A3 = 0x6A289C, A4 = 0x5E4880

Which one of the following is TRUE?
A
A1 and A4 are mapped to different cache sets.
B
A1 and A3 are mapped to the same cache set.
C
A3 and A4 are mapped to the same cache set.
D
A2 and A3 are mapped to the same cache set.
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