1
GATE CSE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
A
Width of tag comparator
B
Width of set index decoder
C
Width of way selection multiplexor
D
Width of processor to main memory data bus
2
GATE CSE 2014 Set 2
Numerical
+2
-0
A $$4$$-way set-associative cache memory unit with a capacity of $$16KB$$ is built using a block size of $$8$$ words. The word length is $$32$$ bits. The size of the physical address space is $$4$$ $$GB.$$ The number of bit for the TAG field is ____________.
Your input ____
3
GATE CSE 2014 Set 2
Numerical
+2
-0
Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for $$100$$ nanoseconds ($$ns$$) by the data, address, and control signals. During the same $$100$$ $$ns$$, and for $$500$$ $$ns$$ thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in $$1$$ millisecond is ____________.
Your input ____
4
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
A $$RAM$$ chip has a capacity of $$1024$$ words of $$8$$ bits each $$\left( {1K \times 8} \right).$$ The number of $$2 \times 4$$ decoders with enable line needed to construct a $$16K \times 16\,\,RAM$$ from $$1K \times 8\,\,RAM$$ is
A
$$4$$
B
$$5$$
C
$$6$$
D
$$7$$
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