1
GATE CSE 2014 Set 2
Numerical
+2
-0
A $$4$$-way set-associative cache memory unit with a capacity of $$16KB$$ is built using a block size of $$8$$ words. The word length is $$32$$ bits. The size of the physical address space is $$4$$ $$GB.$$ The number of bit for the TAG field is ____________.
Your input ____
2
GATE CSE 2014 Set 3
Numerical
+2
-0
The memory access time is $$1$$ nanosecond for a read operation with a hit in cache, $$5$$ nanoseconds for a read operation with a miss in cache, $$2$$ nanoseconds for a write operation with a hit in cache and $$10$$ nanoseconds for a write operation with a miss in cache. Execution of a sequence of instructions involves $$100$$ instruction fetch operations, $$60$$ memory operand read operations and $$40$$ memory operand write operations. The cache hit-ratio is $$0.9.$$ The average memory access time (in nanoseconds) in executing the sequence of instructions is___________________.
Your input ____
3
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
A $$RAM$$ chip has a capacity of $$1024$$ words of $$8$$ bits each $$\left( {1K \times 8} \right).$$ The number of $$2 \times 4$$ decoders with enable line needed to construct a $$16K \times 16\,\,RAM$$ from $$1K \times 8\,\,RAM$$ is
4
GATE CSE 2012
MCQ (Single Correct Answer)
+2
-0.6
A computer has a $$256$$ $$K$$ Byte, $$4$$-way set associative, write back data cache with block size of $$32$$ Bytes. The processor sends $$32$$ bit addresses to the cache controller. Each cache tag director $$y$$ entry contains, in addition to address tag, $$2$$ valid bits. $$1$$ modified bit and $$1$$ replacement bit.
The size of the cache tag directory is
Questions Asked from Memory Interfacing (Marks 2)
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