1
GATE CSE 2014 Set 2
Numerical
+2
-0
A $$4$$-way set-associative cache memory unit with a capacity of $$16KB$$ is built using a block size of $$8$$ words. The word length is $$32$$ bits. The size of the physical address space is $$4$$ $$GB.$$ The number of bit for the TAG field is ____________.
Your input ____
2
GATE CSE 2014 Set 2
MCQ (Single Correct Answer)
+2
-0.6
If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected?
A
Width of tag comparator
B
Width of set index decoder
C
Width of way selection multiplexor
D
Width of processor to main memory data bus
3
GATE CSE 2013
MCQ (Single Correct Answer)
+2
-0.6
A $$RAM$$ chip has a capacity of $$1024$$ words of $$8$$ bits each $$\left( {1K \times 8} \right).$$ The number of $$2 \times 4$$ decoders with enable line needed to construct a $$16K \times 16\,\,RAM$$ from $$1K \times 8\,\,RAM$$ is
A
$$4$$
B
$$5$$
C
$$6$$
D
$$7$$
4
GATE CSE 2012
MCQ (Single Correct Answer)
+2
-0.6
A computer has a $$256$$ $$K$$ Byte, $$4$$-way set associative, write back data cache with block size of $$32$$ Bytes. The processor sends $$32$$ bit addresses to the cache controller. Each cache tag director $$y$$ entry contains, in addition to address tag, $$2$$ valid bits. $$1$$ modified bit and $$1$$ replacement bit.

The number of bit in the tag field of an address is

A
$$11$$
B
$$14$$
C
$$16$$
D
$$27$$
GATE CSE Subjects
Software Engineering
Web Technologies
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