1
GATE CSE 2004
MCQ (Single Correct Answer)
+2
-0.6
A $$4$$-stage pipeline has the stage delays as $$150, 120,160$$ and $$140$$ nano seconds respectively. Registers that are used between the stages have a delay of $$5$$ nanoseconds each. Assuming constant clocking rate, the total time taken to process $$1000$$ data items on this pipeline will be
A
$$120.4$$ microseconds
B
$$160.5$$ microseconds
C
$$165.5$$ microseconds
D
$$590.0$$ microseconds
2
GATE CSE 2002
MCQ (Single Correct Answer)
+2
-0.6
The performance of a pipelined processor suffers if
A
The pipeline stages have different delays
B
Consecutive instructions are depend on each other
C
The pipeline stages share single hardware resources
D
All of the above
GATE CSE Subjects
Software Engineering
Web Technologies
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