1
GATE CSE 2010
MCQ (Single Correct Answer)
+2
-0.6
A $$5$$-stage pipelined processor has Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ Perform Operation $$(PO)$$ and Write Operand $$(WO)$$ stages. The $$IF, ID, OF$$ and $$WO$$ stages take $$1$$ clock cycle each for any instruction. The $$PO$$ stage takes $$1$$ clock cycle for $$ADD$$ and $$SUB$$ instructions, $$3$$ clock cycles for $$MUL$$ instruction, and $$6$$ clock cycles for $$DIV$$ instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? GATE CSE 2010 Computer Organization - Pipelining Question 27 English
A
$$13$$
B
$$15$$
C
$$17$$
D
$$19$$
2
GATE CSE 2009
MCQ (Single Correct Answer)
+2
-0.6
Consider a $$4$$ stage pipeline processor. The number of cycles needed by the four instructions $${\rm I}1,$$ $${\rm I}2,$$ $${\rm I}3,$$ $${\rm I}4,$$ in stages $$S1, S2, S3, S4$$ is shown below. GATE CSE 2009 Computer Organization - Pipelining Question 28 English

What is the number of cycles needed to execute the following loop?
For $$\left( {i = 1} \right.$$ to $$\left. 2 \right)$$ $$\left\{ {{\rm I}1;{\rm I}2;{\rm I}3;{\rm I}4;} \right\}$$

A
$$16$$
B
$$23$$
C
$$28$$
D
$$30$$
3
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
$$1.\,\,\,\,$$ Function locals and parameters
$$2.\,\,\,\,$$ Register saves and restores
$$3.\,\,\,\,$$ Instruction fetches
A
$$1$$ only
B
$$2$$ only
C
$$3$$ only
D
$$1,2$$ and $$3$$
4
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
The following code is to run on a pipelined processor with one branch delay slot
$$\eqalign{ & {{\rm I}_1}:\,\,ADD\,\,{R_2}\,\, \leftarrow \,\,{R_7} + {R_8} \cr & {{\rm I}_2}:\,\,SUB\,\,\,{R_4}\,\, \leftarrow \,\,{R_5} - {R_6} \cr & {{\rm I}_3}:\,\,ADD\,\,{R_1}\,\, \leftarrow \,\,{R_2} + {R_3} \cr & {{\rm I}_4}:\,\,STORE\,\,Memory\,\,\left[ {{R_4}} \right]\,\, \leftarrow \,\,{R_1} \cr & BRANCH\,\,to\,\,Label\,\,if\,\,{R_1} = = 0 \cr} $$

Which of the instructions $${{\rm I}_1},\,{{\rm I}_2},\,{{\rm I}_3}$$ or $${{\rm I}_4}$$ can legitimately occupy the delay slot without any other program modification?

A
$${{\rm I}_1}$$
B
$${{\rm I}_2}$$
C
$${{\rm I}_3}$$
D
$${{\rm I}_4}$$
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