1
GATE CSE 2011
MCQ (Single Correct Answer)
+2
-0.6
Consider an instruction pipeline with four stages $$\left( {S1,\,S2,\,S3,} \right.$$ and $$\left. {S4} \right)$$ each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.
![GATE CSE 2011 Computer Organization - Pipelining Question 23 English](https://imagex.cdn.examgoal.net/sUSo1jSGBLQNIEVg5/rExK51MhCzRSUQhauCo6y5XoKy0mQ/ZxsYQVcIjWBC320XGjwusI/uploadfile.jpg)
What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?
2
GATE CSE 2010
MCQ (Single Correct Answer)
+2
-0.6
A $$5$$-stage pipelined processor has Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ Perform Operation $$(PO)$$ and Write Operand $$(WO)$$ stages. The $$IF, ID, OF$$ and $$WO$$ stages take $$1$$ clock cycle each for any instruction. The $$PO$$ stage takes $$1$$ clock cycle for $$ADD$$ and $$SUB$$ instructions, $$3$$ clock cycles for $$MUL$$ instruction, and $$6$$ clock cycles for $$DIV$$ instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?
![GATE CSE 2010 Computer Organization - Pipelining Question 24 English](https://gateclass.static.cdn.examgoal.net/xe2D8RcnuEva1x4BO/1IqbDElGeaUWn6ok5A3MuwY7QEdKA/zFBjLLQHS3GXcgyPjNSevz/uploadfile.jpg)
![GATE CSE 2010 Computer Organization - Pipelining Question 24 English](https://gateclass.static.cdn.examgoal.net/xe2D8RcnuEva1x4BO/1IqbDElGeaUWn6ok5A3MuwY7QEdKA/zFBjLLQHS3GXcgyPjNSevz/uploadfile.jpg)
3
GATE CSE 2009
MCQ (Single Correct Answer)
+2
-0.6
Consider a $$4$$ stage pipeline processor. The number of cycles needed by the four instructions $${\rm I}1,$$ $${\rm I}2,$$ $${\rm I}3,$$ $${\rm I}4,$$ in stages $$S1, S2, S3, S4$$ is shown below.
![GATE CSE 2009 Computer Organization - Pipelining Question 25 English](https://gateclass.static.cdn.examgoal.net/ZOauUn1gi9FDkcYm9/HYHx1oSNuKkbg3baC5Zd3Y6cD1Yog/ZJm8CNrwdRwBHRw3GJ6eD4/uploadfile.jpg)
What is the number of cycles needed to execute the following loop?
For $$\left( {i = 1} \right.$$ to $$\left. 2 \right)$$ $$\left\{ {{\rm I}1;{\rm I}2;{\rm I}3;{\rm I}4;} \right\}$$
4
GATE CSE 2008
MCQ (Single Correct Answer)
+2
-0.6
The following code is to run on a pipelined processor with one branch delay slot
$$\eqalign{ & {{\rm I}_1}:\,\,ADD\,\,{R_2}\,\, \leftarrow \,\,{R_7} + {R_8} \cr & {{\rm I}_2}:\,\,SUB\,\,\,{R_4}\,\, \leftarrow \,\,{R_5} - {R_6} \cr & {{\rm I}_3}:\,\,ADD\,\,{R_1}\,\, \leftarrow \,\,{R_2} + {R_3} \cr & {{\rm I}_4}:\,\,STORE\,\,Memory\,\,\left[ {{R_4}} \right]\,\, \leftarrow \,\,{R_1} \cr & BRANCH\,\,to\,\,Label\,\,if\,\,{R_1} = = 0 \cr} $$
$$\eqalign{ & {{\rm I}_1}:\,\,ADD\,\,{R_2}\,\, \leftarrow \,\,{R_7} + {R_8} \cr & {{\rm I}_2}:\,\,SUB\,\,\,{R_4}\,\, \leftarrow \,\,{R_5} - {R_6} \cr & {{\rm I}_3}:\,\,ADD\,\,{R_1}\,\, \leftarrow \,\,{R_2} + {R_3} \cr & {{\rm I}_4}:\,\,STORE\,\,Memory\,\,\left[ {{R_4}} \right]\,\, \leftarrow \,\,{R_1} \cr & BRANCH\,\,to\,\,Label\,\,if\,\,{R_1} = = 0 \cr} $$
Which of the instructions $${{\rm I}_1},\,{{\rm I}_2},\,{{\rm I}_3}$$ or $${{\rm I}_4}$$ can legitimately occupy the delay slot without any other program modification?
Questions Asked from Pipelining (Marks 2)
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