1

GATE CSE 2020

Numerical

+2

-0.67

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is _____.

Your input ____

2

GATE CSE 2018

Numerical

+2

-0

The instruction pipeline of a $$RISC$$ processor has the following stages: Instruction Fetch $$(IF),$$ Instruction Decode $$(ID),$$ Operand Fetch $$(OF),$$ Perform Operation $$(PO)$$ and Writeback $$(WB).$$ The $$IF,$$ $$ID,$$ $$OF$$ and $$WB$$ stages take $$1$$ clock cycle each for every instruction. Consider a sequence of $$100$$ instructions. In the $$PO$$ stage, $$40$$ instructions take $$3$$ clock cycles each, $$35$$ instructions take $$2$$ clock cycles each, and the remaining $$25$$ instructions take $$1$$ clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is ______.

Your input ____

3

GATE CSE 2016 Set 2

Numerical

+2

-0

Suppose the functions $$F$$ and $$G$$ can be computed in $$5$$ and $$3$$ nanoseconds by functional units $${U_F}$$ and $${U_G},$$ respectively. Given two instances of $${U_F}$$ and two instances of $${U_G},$$ it is required to implement the computation $$F\left( {G\left( {{X_i}} \right)} \right)$$ for $$1 \le i \le 10.$$ Ignoring all other delays, the minimum time required to complete this computation is _____________ nanoseconds.

Your input ____

4

GATE CSE 2016 Set 2

Numerical

+2

-0

Consider a $$3$$ $$GHz$$ (gigahertz) processor with a three-stage pipeline and stage latencies $${\tau _1},{\tau _2},$$ and $${\tau _3}$$ such that $${\tau _1} = 3{\tau _2}/4 = 2{\tau _3}.$$ If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is ____________ $$GHz,$$ ignoring delays in the pipeline registers.

Your input ____

Questions Asked from Pipelining (Marks 2)

Number in Brackets after Paper Indicates No. of Questions

GATE CSE 2021 Set 1 (2)
GATE CSE 2020 (1)
GATE CSE 2018 (1)
GATE CSE 2016 Set 2 (2)
GATE CSE 2016 Set 1 (1)
GATE CSE 2015 Set 1 (1)
GATE CSE 2015 Set 2 (1)
GATE CSE 2015 Set 3 (1)
GATE CSE 2014 Set 1 (1)
GATE CSE 2014 Set 3 (2)
GATE CSE 2013 (1)
GATE CSE 2011 (1)
GATE CSE 2010 (1)
GATE CSE 2009 (1)
GATE CSE 2008 (4)
GATE CSE 2007 (1)
GATE CSE 2006 (1)
GATE CSE 2005 (1)
GATE CSE 2004 (1)
GATE CSE 2002 (1)

GATE CSE Subjects

Theory of Computation

Operating Systems

Algorithms

Database Management System

Data Structures

Computer Networks

Software Engineering

Compiler Design

Web Technologies

General Aptitude

Discrete Mathematics

Programming Languages