GATE CSE 2022 | Pipelining Question 2 | Computer Organization

GATE CSE 2022

Numerical

-0.33

A processor X₁ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X₂ operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X₁ and X₂. If the BPU has a prediction accuracy of 90%, the speed up (rounded off to two decimal places) obtained by X₂ over X₁ in executing P is ____________.

Your input ____

GATE CSE 2012

MCQ (Single Correct Answer)

-0.3

as an alternative to register allocation at compile time

for efficient access to function parameters and local variables

to handle certain kinds of hazards

as part of address translation

GATE CSE 2003

MCQ (Single Correct Answer)

-0.3

For a pipelined $$CPU$$ with a single $$ALU$$, consider the following situations
$$1.\,\,\,\,\,$$ The $$j+1$$ instruction uses the result of the $$j$$-$$th$$ instruction as an operand
$$2.\,\,\,\,\,$$ The execution of a conditional jump instruction
$$3.\,\,\,\,\,$$ The $$j$$-$$th$$ and $$j+1$$ instruction require the $$ALU$$ at the same time

Which of the above can cause a hazard?

$$1$$ and $$2$$ only

$$2$$ and $$3$$ only

$$3$$ only

ALL the three

GATE CSE 2000

MCQ (Single Correct Answer)

-0.3

Comparing the time $$T1$$ taken for a single instruction on a pipelined $$CPU$$ with time $$T2$$ taken on a non-pipelined but identical $$CPU,$$ we can say that

$$T1 \le T2$$

$$T1 \ge T2$$

$$T1 < T2$$

$$T1$$ is $$T2$$ plus the time taken for one instruction fetch cycle