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1

### GATE CSE 2009

Consider a $$4$$ stage pipeline processor. The number of cycles needed by the four instructions $${\rm I}1,$$ $${\rm I}2,$$ $${\rm I}3,$$ $${\rm I}4,$$ in stages $$S1, S2, S3, S4$$ is shown below.

What is the number of cycles needed to execute the following loop?
For $$\left( {i = 1} \right.$$ to $$\left. 2 \right)$$ $$\left\{ {{\rm I}1;{\rm I}2;{\rm I}3;{\rm I}4;} \right\}$$

A
$$16$$
B
$$23$$
C
$$28$$
D
$$30$$
2

### GATE CSE 2008

Which of the following are NOT true in a pipelined processor?
$$1.$$ Bypassing can handle all RAW hazards
$$2.$$ Register renaming can eliminate all register carried WAR hazards
$$3.$$ Control hazard penalties can be eliminated by dynamic branch prediction.
A
$$1$$ and $$2$$ only
B
$$1$$ and $$3$$ only
C
$$2$$ and $$3$$ only
D
$$1,2$$ and $$3$$
3

### GATE CSE 2008

In an instruction execution pipeline, the earliest that the data $$TLB$$ (Translation Look aside Buffer) can be accessed is
A
Before effective address calculation has started
B
C
After effective address calculation has completed
D
After data cache lookup has completed
4

### GATE CSE 2008

The following code is to run on a pipelined processor with one branch delay slot
\eqalign{ & {{\rm I}_1}:\,\,ADD\,\,{R_2}\,\, \leftarrow \,\,{R_7} + {R_8} \cr & {{\rm I}_2}:\,\,SUB\,\,\,{R_4}\,\, \leftarrow \,\,{R_5} - {R_6} \cr & {{\rm I}_3}:\,\,ADD\,\,{R_1}\,\, \leftarrow \,\,{R_2} + {R_3} \cr & {{\rm I}_4}:\,\,STORE\,\,Memory\,\,\left[ {{R_4}} \right]\,\, \leftarrow \,\,{R_1} \cr & BRANCH\,\,to\,\,Label\,\,if\,\,{R_1} = = 0 \cr}

Which of the instructions $${{\rm I}_1},\,{{\rm I}_2},\,{{\rm I}_3}$$ or $${{\rm I}_4}$$ can legitimately occupy the delay slot without any other program modification?

A
$${{\rm I}_1}$$
B
$${{\rm I}_2}$$
C
$${{\rm I}_3}$$
D
$${{\rm I}_4}$$

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