A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

In the circuit shown in Figure, A is a parallel in, parallel-out 4-bit register, which loads at the rising edge of the clock C. The input lines are connected to a 4-bit bus, W. Its output acts as the input to a 16×4 ROM whose output is floating when the enable input E is 0. A partial table of the contents of the ROM is as follows

The clock to the register is shown, and the data on the W bus at time t$$_1$$ is 0110. The data on the bus at time t$$_2$$ is

With out any additional circuitry, an 8:1 MUX can be used to obtain

The circuit shown in figure has 4 boxes each described by inputs P, Q, R and outputs Y, Z with
Y = $$\,P \oplus \,Q\, \oplus \,R$$
z= $$RQ + \overline P R\, + Q\,\overline P $$ The circuit acts as a