The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns

The circuit shown in figure is a 4-bit DAC The input bits 0 and 1 are represented by 0 and 5 V respectively. The OP- AMP is ideal, but all the resistances and the 5V inputs have a tolerance of ±10%.
The specification (rounded to the nearest multiple of 5%) for the tolerance of the DAC is

The unit of $$\nabla\times\mathrm H$$ is

If the electric field intensity is given by $$\mathrm E=\left(\mathrm x{\widehat{\mathrm u}}_\mathrm x\;+\mathrm y{\widehat{\mathrm u}}_\mathrm y+\mathrm z{\widehat{\mathrm u}}_\mathrm z\right)\;\mathrm{volt}/\mathrm m$$, the potential difference between X(2,0,0) and Y(1,2,3) is