The root locus of the system $$$G\left(s\right)H\left(s\right)=\frac K{s\left(s+2\right)\left(s+3\right)}$$$ has the break-away point located at

The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns

The output of the 74 series of TTL gates is taken from a BJT in

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then