The circuit shown in figure is a 4-bit DAC The input bits 0 and 1 are represented by 0 and 5 V respectively. The OP- AMP is ideal, but all the resistances and the 5V inputs have a tolerance of ±10%.
The specification (rounded to the nearest multiple of 5%) for the tolerance of the DAC is

The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns

The output of the 74 series of TTL gates is taken from a BJT in

A 4 bit ripple counter and a 4 bit synchronous counter are made using flip-flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then