The simplified block diagram of a $$10$$-bit $$A/D$$ converter of dual slope integrator type is shown in Fig. The $$10$$-bit counter at the output is clocked by a $$1$$ $$MHz$$ clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this $$A/D$$ converter is approximately. Input sample to be converter

For a dual $$ADC$$ type $$3\,{\raise0.5ex\hbox{$\scriptstyle 1$} \kern-0.1em/\kern-0.15em \lower0.25ex\hbox{$\scriptstyle 2$}}$$ digit $$DVM$$, the reference voltage is $$100$$ $$mV$$ and the first integration time is set to $$300$$ $$ms$$. For some input voltage, the ''deintegration'' period is $$370.2ms.$$ The $$DVM$$ will indicate.