An $$8$$-bit, unipolar Successive Approximation Register type $$ADC$$ is used to convert $$3.5$$ $$V$$ to digital equivalent output. The reference voltage is $$+5 V.$$ The output of the $$ADC,$$ at the end of $$3$$rd clock pulse after the start of conversion, is

A student has made a-$$3$$ bit binary down counter and connected to the $$R$$-$$2R$$ ladder type $$DAC$$ [Gain $$=$$ $$\left( { - 1k\Omega /2R} \right)$$ as shown in figure to generate a staircase waveform.

The output achieved is different as shown in figure. What could be the possible cause of this error?

A digital-to-analog converter with a full -scale output voltage of $$3.5$$ $$V$$ has a resolution close to $$14$$ $$m$$ $$V.$$ Its bit size is

The simplified block diagram of a $$10$$-bit $$A/D$$ converter of dual slope integrator type is shown in Fig. The $$10$$-bit counter at the output is clocked by a $$1$$ $$MHz$$ clock. Assuming negligible timing overhead for the control logic, the maximum frequency of the analog signal that can be converted using this $$A/D$$ converter is approximately. Input sample to be converter