A programmable logic array (PLA) is shown in the figure. The Boolean function F implemented is

Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to the 4-bit adder are initially reset to 0. At t=0, the inputs to the 4-bit adder are changed to $${X_3}$$$${X_2}$$$${X_1}$$$${X_0}$$ =1100, $${Y_3}$$$${Y_2}$$$${Y_1}$$$${Y_0}$$ = 0100 and $${Z_0}$$=1. The output of the ripple carry adder will be stable at t (in ns) = ____

A two wire transmission line terminates in a television set. The VSWR measured on the line is 5.8. The percentage of power that is reflected from the television set is

Standard air filled rectangular waveguides of dimensions a = 2.29cm and b = 1.02cm are designed for radar applications. It is desired that these waveguides operate only in the dominant $$T{E_{10}}$$ mode with the operating frequency at least 25% above the cut-off frequency of the $$T{E_{10}}$$ mode but not higher than 95% of the next higher cutoff frequency. The range of the allowable operating frequency f is