Consider the state space realization $$$\left[ {\matrix{ {\mathop x\limits^ \bullet } & {\left( t \right)} \cr {\mathop x\limits^ \bullet } & {\left( t \right)} \cr } } \right] = \left[ {\matrix{ 0 & 0 \cr 0 & { - 9} \cr } } \right]\left[ {\matrix{ {{x_1}} & {\left( t \right)} \cr {{x_2}} & {\left( t \right)} \cr } } \right] + \left[ {\matrix{ 0 \cr {45} \cr } } \right]u\left( t \right),$$$ with the initial condition $$\left[ {\matrix{ {{x_1}} & {\left( 0 \right)} \cr {{x_2}} & {\left( 0 \right)} \cr } } \right] = \left[ {\matrix{ 0 \cr 0 \cr } } \right];$$
Where u(t) denotes the unit step function.
The value of $$\mathop {Lt}\limits_{x \to \infty } \left| {\sqrt {{x_1}^2\left( t \right) + {x_2}^2\left( t \right)} } \right|$$ is ______

Consider the circuit shown in the figure. The Boolean expression F implemented by the circuit is

A programmable logic array (PLA) is shown in the figure. The Boolean function F implemented is

Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to the 4-bit adder are initially reset to 0. At t=0, the inputs to the 4-bit adder are changed to $${X_3}$$$${X_2}$$$${X_1}$$$${X_0}$$ =1100, $${Y_3}$$$${Y_2}$$$${Y_1}$$$${Y_0}$$ = 0100 and $${Z_0}$$=1. The output of the ripple carry adder will be stable at t (in ns) = ____