1
GATE ECE 2017 Set 2
Numerical
+1
-0
Consider the state space realization $$$\left[ {\matrix{ {\mathop x\limits^ \bullet } & {\left( t \right)} \cr {\mathop x\limits^ \bullet } & {\left( t \right)} \cr } } \right] = \left[ {\matrix{ 0 & 0 \cr 0 & { - 9} \cr } } \right]\left[ {\matrix{ {{x_1}} & {\left( t \right)} \cr {{x_2}} & {\left( t \right)} \cr } } \right] + \left[ {\matrix{ 0 \cr {45} \cr } } \right]u\left( t \right),$$$ with the initial condition $$\left[ {\matrix{ {{x_1}} & {\left( 0 \right)} \cr {{x_2}} & {\left( 0 \right)} \cr } } \right] = \left[ {\matrix{ 0 \cr 0 \cr } } \right];$$
Where u(t) denotes the unit step function.
The value of $$\mathop {Lt}\limits_{x \to \infty } \left| {\sqrt {{x_1}^2\left( t \right) + {x_2}^2\left( t \right)} } \right|$$ is ______
Your input ____
2
GATE ECE 2017 Set 2
Numerical
+2
-0
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0. GATE ECE 2017 Set 2 Digital Circuits - Sequential Circuits Question 21 English

If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is __________.

Your input ____
3
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
In a DRAM,
A
periodic refreshing is not required
B
information is stored in a capacitor
C
information is stored in a latch
D
both read and write operations can be performed simultaneously
4
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
Consider the circuit shown in the figure. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 37 English The Boolean expression F implemented by the circuit is
A
$$\overline X \,\overline Y \,\overline Z + XY + \,\overline Y \,Z$$
B
$$\overline X \,Y\,\overline Z + XZ + \,\overline Y \,Z$$
C
$$\overline X \,Y\,\overline Z + XY + \,\overline Y \,Z$$
D
$$\overline X \,\overline Y \,\overline Z + XZ + \,\overline Y \,Z$$
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