1
GATE ECE 2017 Set 2
Numerical
+2
-0
Figure I shows a 4-bits ripple carry adder realized using full adders and Figure II shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure II are 20 ns, 15 ns and 10 ns respectively. Assume all the inputs to the 4-bit adder are initially reset to 0. GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 15 English 1 GATE ECE 2017 Set 2 Digital Circuits - Combinational Circuits Question 15 English 2 At t=0, the inputs to the 4-bit adder are changed to $${X_3}$$$${X_2}$$$${X_1}$$$${X_0}$$ =1100, $${Y_3}$$$${Y_2}$$$${Y_1}$$$${Y_0}$$ = 0100 and $${Z_0}$$=1. The output of the ripple carry adder will be stable at t (in ns) = ____
Your input ____
2
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
In a DRAM,
A
periodic refreshing is not required
B
information is stored in a capacitor
C
information is stored in a latch
D
both read and write operations can be performed simultaneously
3
GATE ECE 2017 Set 2
Numerical
+2
-0
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0. GATE ECE 2017 Set 2 Digital Circuits - Sequential Circuits Question 18 English

If the input sequence is 10101101001101, starting with the left-most bit, then the number of times 'Out' will be 1 is __________.

Your input ____
4
GATE ECE 2017 Set 2
MCQ (Single Correct Answer)
+1
-0.3
Two conducting spheres S1 and S2 of radii a and b (b>a) respectively, are placed far apart and connected by a long, thin conducting wire, as shown in the figure. GATE ECE 2017 Set 2 Electromagnetics - Maxwell Equations Question 32 English

For some charge placed on this structure, the potential and surface electric field on S1 are Va and Ea , and that on S2 are Vb and Eb, respectively, which of the following is CORRECT?

A
Va = Vb and Ea < Eb
B
Va > Vb and Ea > Eb
C
Va = Vb and Ea > Eb
D
Va > Vb and Ea = Eb
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