Consider an n-channel MOSFET having width W, length L, electron mobility in the channel $$\mu_n$$ and oxide capacitance per unit area $$C_{ox}$$. If gate-to-source voltage V_GS=0.7 V, drain-to source voltage V_DS=0.1V, $$\left(\mu_nC_{ox}\right)\;=\;100\;\mu A/V^2$$, threshold voltage V_TH=0.3 V and (W/L) = 50, then the transconductance g_m (in mA/V) is ___________.

An n-channel enhancement mode MOSFET is biased at V_GS > V_TH and V_DS > (V_GS - V_TH), where V_GS is the gate-to-source voltage, V_DS is the drain-to-source voltage and V_TH is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves as a

For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is

Two n-channel MOSFETs, T1 and T2, are identical in all respects except that the width of T2 is double of T1. Both the transistor are biased in the saturation region of operation, but the gate overdrive voltage (V_GS - V_TH) of T2 is double that of T1, where V_GS and V_TH are the gate-to-source voltage and threshold voltage of the transistors, respectively. If the drain current and transconductance of T1 are I_D1 and g_m1 respectively ; the corresponding values of these two parameters for T2 are